1. Field
Various exemplary embodiments of the present invention relate to a solid state storage system, and more particularly a read-threshold calibration in a solid state storage system.
2. Description of the Related Art
In NAND flash memory storage devices, information is stored in a cell by different charge levels in a cell. During write and read process, noise is introduced by program disturb and inter-cell interference charge leakage that causes the voltage level to drop over time, where the drop is proportional to the amount of charge stored as well as the number of program and erase (P/E) cycles a cell has experienced. Since the noise varies across cells, cells intended to be written to the same voltage level exhibit certain voltage distribution when read back. Usually, the distribution from a higher intended voltage level will drift down and broaden as time passes due to the charge leaking effect, potentially overlapping a part of the distribution from a lower intended voltage level. This drifting and broadening phenomenon is more severe for smaller fabrication process nodes. Consequently, discerning cells that belong to a particular distribution becomes increasingly difficult as NAND flash memory vendors aggressively shrink the fabrication process nodes to increase storage density and reduce cost.
For hard-read NAND flash memory storage devices, reading back the stored information involves comparing the cell voltage against a set of thresholds. In SLC (Single-Level Cell) devices, the read back value of a bit (either 0 or 1) is solely based on whether the cell voltage is above or below a single threshold. (The term “hard-read” refers to the fact that the read back values are either 0 or 1. This is in contrast to the term “soft-read”, where the read back values can take on a range of numbers for representing the cell voltage in a fine resolution.) Ideally, the thresholds should be chosen to minimize the number of bit errors due to two potentially overlapping distributions. However, this is not an easy task as the distributions, which are a function of the intended voltage levels, the number of P/E cycles the cells have gone through, and the data retention period (i.e., the period of time elapsed between writing and reading the data), are not known in advance. Hence, setting the thresholds properly to minimize bit error rate (BER) in an adaptive manner is a critical component in ensuring data reliability in modern NAND flash memory storage devices. In various embodiments, a number of techniques may be used to estimate of optimal threshold. However, in some cases the threshold found by the optimal threshold estimation process may be greatly inaccurate to the real optimal threshold. An improved read-threshold calibration technique using the iterative filtering technique is described herein. The proposed scheme can provide more accurate estimate of the optimal threshold.
Some techniques for locating the optimal threshold try to measure the cell level distribution and use the minimum as the threshold. A drawback to this is that the threshold may be greatly inaccurate to the optimal threshold. In FIG. 1, the distribution is measured from a multi-level cell (MLC) device where two bits are stored per cell. It may be clear that the measured cell level distribution includes a large amount of noise. In this case, techniques which use a minimum will be trapped at some local minimal points and hence far away from the global minimum point.
One previous idea for addressing the (wrong) local minimum points was to increase the step size when measuring the distribution. However, changing the step size does not eliminate those local minimum points. The measurement results using 2×, 3×, 4× and 5× step size are shown in FIG. 2 to FIG. 6. As shown, down-sampling the distribution does not resolve concerns.
The technique described herein aims to fix this weakness.